13
On this processor, the register that holds the conversion result is 16 bits wide.
A right-justified result means that bits [(N-1):0] (where N is the number of bits of precision) of the register contain the ADC value and the most-significant bits of the register are set to zero.
A left-justified result means that bits [15:(16-N)] of the register hold the ...
12
Stack and heap are software concepts, not hardware concepts. What the hardware provides is memory. Defining zones of memory, one of which is called “stack” and one of which is called “heap”, is a choice of your program.
The hardware does help with stacks. Most architectures have a dedicated register called the stack pointer. Its intended use is that when ...
11
This goes way, way back to the Bell 103 modem from 1962. It operated at 300 bits per second for reasons deriving from the use of audio frequency-shift keying to modulate data; the frequencies available were limited by the quality of the phone lines. All common serial data rates since then are integer multiples of this rate.
11
In General
THUMB instructions aren't to my knowledge intrinsically slower than ARM instructions, but rather are more limited in capability. If your code only needs the functionality of THUMB instructions, it will occupy less space than ARM, but would be the same number of instructions and, other things being equal, run at the same speed. If your code needs ...
9
There are many chips that can be configured by choices made in software, which then have a perfectly analogue behaviour that gets altered.
Blocks that work like that go from Analogue Switch arrays and/or Multiplexers all the way past Programmable-Gain amplifiers through to complete integrated chips that have a combination of blocks, such as programmable ...
7
This works for me with Linux 3.9.0 on an x86_64 architecture.
#!/bin/sh
# This assumes the interfaces come up with default names of eth*.
# The interface names may not be correct at this point, however.
# This is just a way to get the PCI addresses of all the active
# interfaces.
PCIADDRLIST=
for dir in /sys/class/net/eth* ; do
[ -e $dir/device ] &&...
7
The least you can do is given by Shannon-Nyquist theorem: to be able to read a signal, you shall sample at least twice its frequency. Here, you can sample at 20MS/s (Mega sample per second). Nevertheless, 2 points for one period is very few, and introduce much jitter on the rebuilt signal.
Your logic analyzer won't share your signal clock. This is a common ...
7
To update your .dts file (that includes the file am335x-bone-common.dtsi) for a pinmux assignment, consult the datasheet to determine which pin(s) are assigned to a function. This is in section 4.3 (broken into subsections per module). Clicking on the hyperlink for a pin (check your package type, ZCE BALL or ZCZ BALL) will take you to the corresponding ...
7
You don't need to fill the page register all in one go.
You begin a page write (i.e. the "Page Program" operation) by writing the Serial Data Input command (0x80), the column address, and the row address. Then you transfer the data to the page register (up to 2112 bytes). This transfer can be broken up into chunks, with any delay between chunks you need.
...
7
The sizes of the stack and heap are defined by your application, not anywhere in the microcontroller's datasheet.
The stack
The stack is used to store the values of local variables inside of functions, the previous values of CPU registers used for local variables (so they can be restored on exit from the function), the program address to return to when ...
7
You should definitely consider X-rays as a possible source.
An erased flash is full of 1s. Programming a flash is full of 0s. Over time, or under some stress, flash components may lose their gate charge, which leads to 0 to 1 transition. This is a well known behavior on NAND flash, but may also happen on NOR flash, even if those ones are much more robust by ...
6
Quadrature decoder
Looking at the PSoC 4 TCPWM datasheet the maximum operating frequency of the counter block is 48MHz, with a counter resolution of 21ns.
Assuming that you have a high resolution incremental rotary encoder with 10,000 counts per revolution, and spin the rotor at 15,000 rpm, that's 2,500,000 counts per second (2.5MHz), comfortably less than ...
6
You can increase the effective resolution by intentionally oversampling the input signal. Here is brief summary of the idea from an application note on the topic provided by Atmel:
The theory behind ‘Oversampling and decimation’ is rather complex, but using the method is fairly easy. The technique requires a higher amount of samples. These extra samples ...
6
The generic term for multi-core systems that run different kernels (or bare metal code) on different cores is Asymmetric multi-processing (AMP). Other related terms are Heterogeneous Computing, which refers to multiple cores of different types in the same system, and Multiprocessor System-on-Chip (MPSoC).
Freescale happens to have an overview document (PDF) ...
6
It does, unfortunately depend a little on the FPGA itself.
But most cases that will probably not work, unfortunately. In many logic chips with programmable I/O type pins, the final stage looks a bit like this:
This is both a side-effect of the cheapest to make final stage and for protection.
Now if you turn off the power to that stage, the Vdd/Vcc ...
5
The input from the PC is a character, i.e. an ASCII-value. To understand how this is saved, have a look at the ASCII-table. The numbers '0' to '9' are represented by the ASCII-codes 0x30 to 0x39. The capital letters 'A' to 'Z' are represented by 0x41 to 0x5A, and the small letters 'a' to 'z' by 0x61 to 0x7A.
You could of course use a function like sscanf, ...
5
This is due to the design of their SPI peripheral. In slave mode, the shift register is shifted each SPCK (assuming NSS is low and SPIENS is set). There is an internal counter (not shown in the block diagram) for the shift register, and when it reaches the word size, the contents are shifted to SPI_RDR and from SPI_TDR. Thus if you have a word size of 8, ...
5
I have done something similar with a small 8-bit microcontroller in a medical device. The factory had two pieces of firmware:
First, factory test firmware is downloaded. It has the algorithms for exercising the subassembly and talking to the factory test equipment. Factory test are performed.
Second, field firmware is downloaded. Field firmware has its ...
5
In addition to the other answers, I'd like to add that when carving up RAM between stack and heap space, that you also need to consider the space for static non-constant data (e.g. file globals, function statics, and program-wide globals from a C perspective, and probably others for C++).
How stack/heap allocation works
It is worth noting that the startup ...
5
No, at least not in any remotely modern version of Windows.
Accessing hardware directly requires kernel privilege level, which ordinary application programs don't have. Think about it. It has to be this way else one rogue process could cause all kinds of harm.
Drivers not only deal with the hardware details for you, but they also act as gate keeper to ...
4
I think what you're looking for is the ASF Conversion Wizard. According to the linked page, this wizard is supposed to be launched whenever the ASF version changes. If is not launching for you, you can open the ASF Wizard in your existing project, and under the Version tab, you can change the ASF version for your current project. Make sure the "Trigger ...
4
It is used for BCD arithmetic. Each decimal requires 4 bits.
4
It depends a bit on the quality you expect from some of the peripherals and what their qualities are at given clock speeds.
Will you want a very high speed SPI interface and can this specific chip support that on the Fast Auxiliary Clock? Or are you going to do 1MHz SPI at most? So also for all the other devices.
It's of course a nice boasting thing to be ...
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