I was studying with a book named "Digital design and computer architecture".
When I read the part of metastability, it stated this without any additional explanation..
Why does a metastable state eventually resolve to 0 or 1?
I learned that D-flipflop captures signals only when it is CLK posedge.
So I thought that D-flipflop must remain the metastable state until the next CLK posedge but this book says "no" and I want to know why.