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I was studying with a book named "Digital design and computer architecture".
When I read the part of metastability, it stated this without any additional explanation..
Why does a metastable state eventually resolve to 0 or 1?
I learned that D-flipflop captures signals only when it is CLK posedge.
So I thought that D-flipflop must remain the metastable state until the next CLK posedge but this book says "no" and I want to know why.
In any real system there is noise. A metastable state is highly unstable, so random noise in the system will eventually tip the state slightly one way or the other.
The image you show is a little misleading because the hill is flat on top. A better analogy is a ball balanced on a knife edge...possible, but it won't stay that way for long.
Consider an RS flip-flop with both the set and clear inputs asserted. If they're simultaneously negated and one of the gates is a little faster than the other the flip-flop output can oscillate. It can also happen when one of the inputs is slightly ahead of the other. It only lasts for a few cycles, and the end state is unpredictable. It's theoretically possible for the state to last forever, just like it's possible to balance a marble on a needle, but it doesn't happen. It definitely is an important design consideration, though. If a flip-flop has an input that isn't synchronized with its clock, it will occasionally have a short burst of pulses on its output.
