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In cascade PID control loops as below, can I make an assumption that the inner loop will respond much faster than the outer loop, hence I could simplify U1_CMD as U1 and I could design/tune the gains of the outer loop controller without knowing the details of the inner loop controller or the plant model?

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  • $\begingroup$ Yes, but take the time to verify your assumption that the inner loop is faster. Also look at any peaking in the inner loop's CL frequency response. In the archetypical PID closed loop response, a dominant pole plant results in a zero and two poles for the closed loop. When that zero is in the passband, it will have a noticeable effect. // If you are implementing both loops digitally, have the inner loop detect and signal its output saturation (separately for each direction) and use these signals to suppress the outer loop's integrator ramping in the corresponding direction. $\endgroup$
    – Pete W
    Sep 27 at 12:34
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Maybe?

Without knowing ourselves anything about the system you have, it's mostly impossible for us to be able to answer the question.

However, I can say that in general it is certainly possible to consider the inner (stable) control loop to be continuous (namely fast enough) that you could simply consider it part of your system, and run an outer control loop and ignore those dynamics.

I have done this with many current and speed controllers for BLDC motors. They ran a PI controller at 1khz internally, while I ran an LQR controller at 50hz it without issues.

However this doesn't mean that instabilities won't arise, if your outer controller saturates your inner (or vice versa), you're still doomed to instability. You will have to simulate your inner control loop accurately as well as your outer to get an idea if it'll work.

If you can give more of your system info we can help more.

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  • $\begingroup$ Thanks and what do you mean by "your outer controller saturates your inner", could I have an example? $\endgroup$
    – LHX
    Sep 29 at 13:12
  • $\begingroup$ Imagine what would happen if in my example, the internal speed controller has a upper speed limit, but my outter controller wants to do double that or vice versa, my inner controller wants to do a specific speed and the outter limits the available voltage $\endgroup$
    – morbo
    Sep 29 at 13:13
  • $\begingroup$ Thanks again and what instability issue will I have and could adding a limit to the outer-loop output(U1_CMD)eliminate the issue? $\endgroup$
    – LHX
    Sep 29 at 13:27
  • $\begingroup$ @LHX read my very last sentence, no-one can help you do engineering work, without engineering info. $\endgroup$
    – morbo
    Sep 29 at 13:27

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