I2C buses are frequently exposed via a 4-pin connector that carries ground, power, SDA, and SCL. The power is generally supposed to be 3.3V, but exceptions exist. Pinout examples include QUIIC, STEMMA, and PMOD.

I assume that I2C masters (typically development boards containing a microcontroller) will supply the power pin. The simple peripherals may choose to utilize that power, provided sufficient current is available. My question is, are there any standards for the minimum current a master can supply?

Would it be reasonable to create a low-power SoC board that can source only 25mA of 3.3V directly from one of its pins (without an external regulator) and route that to the power pin? Is that enough available power to support an interesting set of low-power (or self-powered) peripherals?

The PSoC 5LP I'm planning on using has a built-in boost regulator so it can run off a wide range of battery voltages.

Example low-power peripheral: Sparkfun CCS811/BME280 (Qwiic) Environmental Combo Breakout Board. The CSS811 has a peak current draw of 56 mA, but the average over a measurement cycle is only 0.7 mA. Can a capacitor in the power line carry the peak load if I can only supply 25mA?

The board's schematic shows a 1uF cap and 0.1uF cap for decoupling. Interestingly it contains a notation saying someone estimated the average draw at 17 mA (without justification). The BME280 is very low power, less than 1mA in any mode. Is the 1uF cap sufficient to cover the current deficit at a 1Hz sample period? Would I need to augment the capacitors?

I guess I could add a small 3.3 regulator, or even a voltage follower so the uC can vary the I2C bus VCC voltage. Just trying to understand what options are reasonable to keep size & battery consumption low.

  • $\begingroup$ Few basics, 3.3V and GND is not part of the I2C protocol. I2C is only two wires. Reading through your question. It seems like you are trying to daisy chain a bunch of devices. You need to look at the peek current and and steady state current for each device and understand if the power source can support all the device. Let me know if my understanding is correct. $\endgroup$ – Mahendra Gunawardena Apr 14 at 22:44
  • $\begingroup$ Yes, mostly, although the NXP I2C spec is full of references to VDD(s) for pull-up resistors, and open-drain outputs clearly must have something to pull down to. But the question in my mind is mostly about using microcontroller output pins to provide power low-power I2C peripherals, which the I2C spec clearly doesn't address. $\endgroup$ – Burt_Harris Apr 17 at 18:00
  • $\begingroup$ The intend of I2C is be used on PCB boards. This allows to manage cross talk, EMI, EMC etc. For a hobby project using GPIO pins might work, but I have never seen this done. Usually the pull up the VDD is what is common. I also would suggest to use low speed for I2C communication. Good Luck let us know the out come. $\endgroup$ – Mahendra Gunawardena Apr 17 at 20:14

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