I2C buses are frequently exposed via a 4-pin connector that carries ground, power, SDA, and SCL. The power is generally supposed to be 3.3V, but exceptions exist. Pinout examples include QUIIC, STEMMA, and PMOD.
I assume that I2C masters (typically development boards containing a microcontroller) will supply the power pin. The simple peripherals may choose to utilize that power, provided sufficient current is available. My question is, are there any standards for the minimum current a master can supply?
Would it be reasonable to create a low-power SoC board that can source only 25mA of 3.3V directly from one of its pins (without an external regulator) and route that to the power pin? Is that enough available power to support an interesting set of low-power (or self-powered) peripherals?
The PSoC 5LP I'm planning on using has a built-in boost regulator so it can run off a wide range of battery voltages.
Example low-power peripheral: Sparkfun CCS811/BME280 (Qwiic) Environmental Combo Breakout Board. The CSS811 has a peak current draw of 56 mA, but the average over a measurement cycle is only 0.7 mA. Can a capacitor in the power line carry the peak load if I can only supply 25mA?
The board's schematic shows a 1uF cap and 0.1uF cap for decoupling. Interestingly it contains a notation saying someone estimated the average draw at 17 mA (without justification). The BME280 is very low power, less than 1mA in any mode. Is the 1uF cap sufficient to cover the current deficit at a 1Hz sample period? Would I need to augment the capacitors?
I guess I could add a small 3.3 regulator, or even a voltage follower so the uC can vary the I2C bus VCC voltage. Just trying to understand what options are reasonable to keep size & battery consumption low.