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How do I show this is clearly not edge triggered

enter image description here

The truth table for this is as follows

E R S Q notQ
0 0 0 prevQ prevnotQ
0 0 1 prevQ prevnotQ
0 1 0 prevQ prevnotQ
0 1 1 prevQ prevnotQ
1 0 0 prevQ prevnotQ
1 0 1 1 0
1 1 0 0 1
1 1 1 0 0

Edge triggering definition: In edge triggering the circuit becomes active at negative or positive edge of the clock signal. For example if the circuit is positive edge triggered, it will take input at exactly the time in which the clock signal goes from low to high


I'm confused how to show this

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It is clear in the last three lines of your truth table that the R and S inputs directly influence the output when E is high (no edges). Therefore, not edge-triggered.

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