If I have a 10 MHz digital signal, how fast do I need to sample with a logic analyzer to avoid any bit errors? Does the minimum sample rate increase if I want to attach a protocol decoder (e.g. SPI)?

I am aware of the Nyquist-Shannon sampling theorem and the fact that a 10 MHz square wave has significant energy at higher harmonics (30 MHz, 50 MHz, etc.). However, a logic analyzer doesn't need to perfectly sample or reproduce a square wave to know if it is a logic 1 or 0. I'm looking for what is practically necessary to avoid bit errors or protocol decoding errors.

I am using the Saleae Logic Pro 16.


1 Answer 1


The least you can do is given by Shannon-Nyquist theorem: to be able to read a signal, you shall sample at least twice its frequency. Here, you can sample at 20MS/s (Mega sample per second). Nevertheless, 2 points for one period is very few, and introduce much jitter on the rebuilt signal.

Your logic analyzer won't share your signal clock. This is a common case in transmission, and I would advise you to do the same as most UART/SPI/I2C/... interface: take 3 points per state. This allow to filter EMC noise using a majority filter, and, when analyzing, allows to see significant skew between your signals. Please note that the clock of a 10MHz SPI bus goes both high and low every 100ns period, so you need to sample at 6 times your SPI frequency (60MS/s).

60MS/s is common for logical analyzers, and this will allow you to detect excessive skew (between your data and your clock) for most protocols (including SPI). Nonetheless, with a non-symmetric clock (with tHIGH != tLOW), you'll need to sample fast enough to sample the shortest part of the clock. If you clock is HIGH for 1µs and LOW for 9µs, you've got a 100kHz signal, but need 3MS/s.

This answer only considers the signal you want to analyze. For EMC issues, we usually use analog scopes with a sampling frequency 10 times higher than the highest frequency in the system, but it's a bit expensive, and off-topic, considering that the question is to decode an SPI bus.

  • 1
    $\begingroup$ I use 6 time the clock frequency as sampling frequency. 4 times should be enough to see any skew, but in my experience, it is harder to understand when dealing with large rise/fall time. $\endgroup$
    – Jacen
    Commented Aug 5, 2015 at 15:24

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