For example, if there is many floating point operations, it could "rewire" the area of some of its integer units to handle floating point instructions, and vice versa. Or if there isn't too many calculations, but there is many I/O need, it could parallelize its IO better.

As I know, the FPGAs load their HDL code on boot, but to me it seems not really impossible, to make it possible to reload differents parts of a bigger HDL on the need, partially.

Does a such FPGA already exist?


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It seems that such (Xilinx) FPGAs already exist. https://en.wikipedia.org/wiki/Reconfigurable_computing#Partial_re-configuration

In partial reconfiguration, one part of the FPGA continues to run while another part is being reconfigured.


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