It does, unfortunately depend a little on the FPGA itself.
But most cases that will probably not work, unfortunately. In many logic chips with programmable I/O type pins, the final stage looks a bit like this:
This is both a side-effect of the cheapest to make final stage and for protection.
Now if you turn off the power to that stage, the Vdd/Vcc voltage goes to 0V, so the top diode, D2, will conduct towards that. Since I2C is powered with resistors from the power rail in an open-collector type scheme, the diode will easily conduct those few mili-amps away, so damage is very unlikely, but the bus will never see a logic one.
If the FPGA is 1.8V or 2.7V or 3.3V itself, but 5V tolerant on the pins in question, the top diode will not be there and the problem may very well disappear, but other characteristics may still have similar influences. (JFETs that turn on because their biasing disappears at power-off, though highly unlikely, technically possible).
An option would be to break the traces and then (if you want the FPGA again later) to add decent analogue switches. Sometimes traces come along the board in such a way that a simple dual Analogue Switch can be dropped right across a gap you made with the scalpel. I've done that a couple of times. It's not something you'd design in, but for 400kHz I2C there are plenty chips that could do it and as an after-market mod, it's not even the ugliest you could think of.