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It is well known that many error detection, mitigation, and correction methods, such as parity or ECC, have been available in large memory banks, like for RAM, for decades now, and even in CPU caches and sometimes parts of state machines. These are mostly large implementations of sequential logic where single event upsets from cosmic rays have a significant enough chance of causing a lasting bit flip, due to the smaller feature size, density, number of latches, etc. Throughout most of computer history, the combinational logic of the CPU, or small sequential logic like singular latches or registers, have remained unprotected. This is mostly due to the unintentional electrical, logical, and temporal masking effects that are due to the low transistor count, number of logic gates, size of transistors, etc., which has made combinational logic soft errors due to SEUs mostly negligible. Over the past few years, the reduced feature size has become a large concern because it may be making combinational logic errors common enough to be a real problem, so I was wondering if there have been any significant implementations of soft error mitigation or correction in combinational logic circuits or single latches/registers in any consumer-level product, like a CPU or microcontroller? Thank you!

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  • $\begingroup$ It's generally frowned upon to cross-post! From electronics $\endgroup$ – StainlessSteelRat Dec 13 '20 at 21:00
  • $\begingroup$ Oh no, I do not frequently use this website so I didn't know that, I apologize! Would you like me to delete this post from here? $\endgroup$ – user29823 Dec 13 '20 at 22:06
  • $\begingroup$ Yes. It would be better answered on electronics. $\endgroup$ – StainlessSteelRat Dec 13 '20 at 22:29

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