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(a)Z=(B+C')A+B(C+D')+BD

Z=AB+AC'+BC+BD'+BD

Z=AB+A'C+B

Z=B+AC'

(b) A B C|Z

0 0 0|0
0 0 1|0
0 1 0|1
0 1 1|1
1 0 0|1
1 0 1|0
1 1 0|1
1 1 1|1

(c) BC 00 01 11 10

 A 0   |0  |1 |1 |1|

   1   |1  |0 |1 |1|

I was able to complete the 1st 3 Q's i.e.(a),(b),(c).But i didn't understand the last 2 Q's i.e. (d),(e).Can someone give me a hint or push me in the right direction? Thanks in advance

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Question D refers to the fact you can use NAND gates in different combinations to replicate different types of gates. IE to replicate a NOT gate, simply tie the 2 inputs of the NAND gate together, and there you go. This Link details the different connections of NAND gates to replicate your gates. Question E refers to your schematic you'll have made in question D once you've removed any redundant NAND gates, if there are any. Every gate has a propogation delay, or the time it takes for the signal to go from the input pins the the output pin. This is usually in nanoseconds. As the question states it'll take 20ns to go from the input of a gate to the output, simply add up the gates in series to come to the answer.

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