I'm currently learning about how a CPU works on the hardware level and something that keeps coming up is memory organization. From what I've learned (and please, do correct me on anything that is not right), you can have a memory organized in the following two ways:

Byte organized memory: Each address on the address bus points to a memory location where a byte (8 bit) is stored.

Word organized memory: Each address on the address bus points to a memory location where a word (multiple of 8 bit) is stored.

In other words, a byte organized memory can access any memory location that is a byte boundary while a word organized memory can only access memory locations that are a word boundary.

Now here is where I have some trouble. I am studying for a midterm comming up and I am looking at past assignments and the following question comes up:

Given a set of memory modules with 20 bit address and 8 bit data interface. We need to build a byte organized main memory of 4 MB for a 16-bit data architecture CPU.

Now I know that we need to build a main memory using the memory modules given. To start off, we need to find the capacity of each memory module, whicch is given by

2^m * n, where m is the address bus in bits and n is the data bus in bits. This gives a capacity of 2^20*8 = 1MBytes for each memory module.

Now we need to figure out how many memory modules are needed. This is fairly easy and is found as follows: 4MB / 1MB = 4 modules.

Now the part where I don't seem to understand, the memory is supposed to be byte organized, but the data bus out of the main memory is 16 bits. How can I design a byte organized memory if each access yields a word? Doesn't byte organized mean that given an address, it would be possible to access that specific byte in the memory? How is that possible when the memory modules must be designed in a way that yields a 16 bit data bus? Here is the solution for the question. Please explain to me in details why the main memory was designed this way, and how it is possible to access each bytes individually.

Answer: enter image description here

Thank you.

  • $\begingroup$ I'm voting to close this question as off-topic because this level of memory-management detail is better suited to a computer-something.SE group $\endgroup$ Commented Feb 14, 2018 at 18:31
  • $\begingroup$ No, this is a question for electronics.stackexchange.com . There should you re-ask. Btw, the answer is that you need some conversion electronics between the external world and your ram module. All the word-reads and word-writes should be converted by this electronics into two byte-reads and byte-writes. It is not always possible, if there are timing constraints, but anyways the circuit is not very complex. $\endgroup$
    – peterh
    Commented Feb 14, 2018 at 21:51
  • 1
    $\begingroup$ I'm voting to close this question as off-topic because it's better suited to SE Electronics $\endgroup$
    – Fred
    Commented Feb 15, 2018 at 1:53
  • $\begingroup$ The question is about CPU architecture and is related to computer hardware and therefore computer engineering. So I believe that the question is in the right section. $\endgroup$
    – user12377
    Commented Feb 18, 2018 at 11:34

1 Answer 1


If you notice, you need 20 bits to access the 1Mb byte modules.

Byte module

But your processor is word aligned. So 2 1Mb byte modules form a 2Mb word module. The key to understanding how it works is the Misalignment at the bottom.

Misalignment of Word addressed modules

You need 20 bits to access the specific byte aligned memory, but each location is a word or two bytes. So you leave A0 (Address bit 0) out of the memory decoding. Which is shown at the bottom of the drawing.

A20 to A1 (bits 1 .. 20) select your 1Mb of word-aligned memory locations. The misalignment is compensated for in the processor, as in high byte D15-D8 and low byte D7-D0.

Add a second bank and A21 selects upper or lower banks. Which is misleading from the diagram. Both banks are accessed and A21 multiplexs between which bank is accessed.

Other option would be A21 selects between the the two banks by activating chip select. Appropriate bank puts data directly on data bus.

Same approach applies to 32, 64 or 128 memory buses. Leave out the low address bits which are made redundant.

Edit to clarify OP comment.

So by your reasoning, you need to be physically able to access each byte. Thus replicating what is already in the processor.

A 64-bit processor with 8Gbytes of memory fetches 8 bytes/access, so 1G 64-bit locations. Should we expand decoding so each byte can be accessed individually?

What about booleans? Do we access via bits? 64 or 128 bit floats. You have the physical structure of the hardware and data structures, which must optimize throughput through processor.

Let's say you create a structure with a bool, byte, 16 bit integer, byte and a 64 bit float. A compiler for the 16 bit processor may allocate it as float (4 ints), int (2 separate bytes combined), int, and int (bool - 15 bits wasted). So 7 ints.

If you turn the structure into an array, the compiler may allocate each member as 8 ints, so the inherent alignment structure for floats and ints is not disrupted. Another int wasted.

  • $\begingroup$ Thanks for your answer, but I have one question. When they say a processor's main memory is byte organized, does that not mean that you should be able to access any specific bytes by giving an address? Let's say I want to access the memory address 0. I will get a word which represents the byte 0 and byte 1. If I want to access memory address 1, it will give me byte 2 and byte 3, not byte 1 and byte 2. Wouldn't this make the memory word organized and not byte organized? $\endgroup$
    – user12377
    Commented Feb 18, 2018 at 11:31

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