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I was reading about the new Intel Xeon Phi processor on Intel's site

https://software.intel.com/xeon-phi/x200-processor/remote-access

and ones of its features is:

Highly-parallel performance: Features up to 72 cores with deep out-of-order buffers.

I was looking for a basic description of these buffers that highlights maybe their purpose (ie parallelism) and behavior. Are these buffers used in the cache?

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The term "out-of-order" here refers to "out of order execution". e.g. if your program has instruction A, then instruction B, then instruction C, it some situations it may turn out that if you execute them in the order A, C, B (instead of A, B, C), you get the exact same result but the program executes quicker. An example of when this would happen is if instruction B requires data to be fetched from RAM but it will take some time to go fetch the data. Instead of sitting around doing nothing while waiting for the data to arrive, the process can save time by executing instruction C while it is waiting (assuming, of course, that instruction C does not need the result of instruction B). Keeping track of what instructions have been re-ordered in what ways requires some memory space. i.e. the processor needs to remember that it put B on hold while waiting for data, so that it can start back up again when the data is ready. That is the buffers that this is referring to. Note: this is a very simplified explanation. The reality of keeping track of everything is more complicated. See https://en.wikipedia.org/wiki/Out-of-order_execution for some more details.

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