Why is it easier to run an STA on a CPLD than an FPGA?

Question

I am aware that it is easier to run a static timing analysis on a CPLD than a FPGA, but why is this?

Any information would be greatly appreciated.

Answer 1

Basically, a CPLD has far fewer choices in terms of the number of different kinds of paths through which a signal can flow from one register to the next, which means that the job of analyzing all of the different combinations of paths is reduced by many orders of magnitude.